Control Signals - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

TigerSHARC Pipelined Interface
processor can issue an address of a new transaction every cycle and doesn't
need to wait for the data cycle of the first transaction before beginning the
address cycle of the new transaction.

Control Signals

The control signals used in pipelined transactions are listed below.
• – the transaction is read.
RD
• and
WRH
The two signals also indicate which word on the data bus is valid.
• – Indicates the next cycle belongs to the same transaction as
BRST
the current cycle—for example, when accessing a quad-word on a
bus width of 32-bits,
four cycle transaction.
• – Driven by the target slave on the data cycle. If asserted, the
ACK
slave is ready to complete the data cycle; otherwise wait cycles are
generated.
Basic Transaction
The basic pipelined transaction is shown in Figure 5-5 on page 5-17. In
the address cycle, the address is issued with the
both) asserted. The data cycle begins after one to four cycles, as specified
in the target slave configuration and the direction of the transaction. The
delay between the address cycle and the data cycle is the "pipeline depth".
In the data cycle, the data is transferred according to the transaction direc-
tion. If the slave is ready, it asserts the
strobes the data. If the slave is not ready, it deasserts the
delays the data. The exact way the
Cycles" on page 5-23.
5-16
– the transaction is written if one of these is active.
WRL
BRST
is active on the first three cycles of the
or
RD
signal and either drives or
ACK
signal behaves is discussed in "Wait
ACK
ADSP-TS101 TigerSHARC Processor
( , or
WRx WRL WRH
signal and
ACK
Hardware Reference