Dsp Architecture - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

DSP Architecture

SDRAM
MEMORY
Figure 1-4. Multiprocessing Cluster Configuration
DSP Architecture
As shown in Figure 1-1 on page 1-2 and Figure 1-2 on page 1-3, the DSP
architecture consists of two divisions: the DSP core (where instructions
execute) and the I/O peripherals (where data is stored and off-chip I/O is
processed). The following discussion provides a high-level description of
the DSP core and peripherals architecture. More detail on the core appears
in other sections of this reference.
High performance is facilitated by the ability to execute up to four 32-bit
wide instructions per cycle. The TigerSHARC processor uses a variation
of a Static Superscalar™ architecture to allow the programmer to specify
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ADSP-TS101 TigerSHARC Processor
Hardware Reference
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