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Processor Microarchitecture
001
000
RESET
CLOCK
REFERENCE
VOLTAGE
LINK
DEVICES
(4 MAX)
(OPTIONAL)
Figure 5-1. Typical Multiprocessing Cluster Configuration
5-6
ADSP-TS101 #7
ADSP-TS101 #6
ADSP-TS101 #5
ADSP-TS101 #4
ADSP-TS101 #3
ADSP-TS101 #2
ADSP-TS101 #1
BR7–2,0
ID2–0
RESET
ADDR31–0
CLKS/REFS
DATA63–0
LINK
CONTROL
ADSP-TS101 #0
ID2–0
RESET
ADDR31–0
DATA63–0
CLKS/REFS
SCLK_P
BUSLOCK
LCLK_P
S/LCLK_N
V
REF
LCLKRAT2–0
DMAR3–0
SCLKFREQ
IRQ3–0
FLAG3–0
LINK
LXDAT7–0
LXCLKIN
LXCLKOUT
LXDIR
TMR0E
BM
CONTROLIMP2–0
CONTROL
DS2–0
BR1
BR7–1
BR0
RD
WRH/L
ACK
MS1–0
BMS
CPA
DPA
BOFF
BRST
HBR
HBG
MSH
FLYBY
IOEN
MSSD
RAS
CAS
LDQM
HDQM
SDWE
SDCKE
SDA10
ADSP-TS101 TigerSHARC Processor
ADDR
GLOBAL
DATA
MEMORY
OE
AND
PERIPHERALS
WE
(OPTIONAL)
ACK
CS
CS
BOOT
ADDR
EPROM
(OPTIONAL)
DATA
CLOCK
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ADDR
DATA
CS
SDRAM
RAS
MEMORY
CAS
(OPTIONAL)
DQM
WE
CKE
A10
ADDR
DATA
CLK
Hardware Reference
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