Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 146

Processor Microarchitecture
the transaction is completed at this point. If it is a read transaction, the
data read on the external transaction is strobed in the IFIFO and is written
later to its target (defined by the original internal transaction).
ADDR
DATA
INTERNAL
BUS
EXTERNAL WRITE - TIGERSHARC BUS MASTER
INTERNAL
BUS
ADDR
DATA
INTERNAL WRITE - TIGERSHARC BUS SLAVE
DATA
INTERNAL
BUS
DMA WRITE - TIGERSHARC BUS MASTER
Figure 5-2. External Port Architecture
5-8
ADDR
OFIFO
DATA
INTERNAL
IFIFO
BUS
OBUF
DMA CONTROLLER
INTERNAL
OFIFO BUS
ADDR
IFIFO
DATA
OBUF
DMA CONTROLLER
ADDR
ADDR
OFIFO
DATA
IFIFO
INTERNAL
BUS
OBUF
DMA CONTROLLER
ADDR
DATA
DMA CONTROLLER
EXTERNAL READ - TIGERSHARC BUS MASTER
ADDR
DATA
DMA CONTROLLER
INTERNAL READ - TIGERSHARC BUS SLAVE
DATA
DMA CONTROLLER
DMA READ - TIGERSHARC BUS MASTER
ADSP-TS101 TigerSHARC Processor
Hardware Reference
OFIFO
ADDR
IFIFO
DATA
OBUF
OFIFO
IFIFO
ADDR
OBUF
DATA
ADDR
ADDR
OFIFO
IFIFO
DATA
OBUF