Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 130

Interrupt Service
• Capture PC in order to store it in
reaches EX2.
!
Storing PC in
interrupt routine reaches EX2 with
step 4 (below) conditions are met.
• Execute instructions in pipeline, unless it encounters an
exception or emulation condition.
3. ISR @ EX2: Is
• If NO then flush pipeline, abort interrupt, and wait for next
instruction.
4. If YES:
•
ILATN
•
PMASK60
PMASK_R59–0
• Exceptions and emulation conditions are not affected by
PMASK60
5. If nesting, for hardware interrupt and
• Store context
• Store
!
Instructions for storing context and
the software.
6. Execute
4-18
happens only after the first instruction of the
RETI
AND NOT
IMASK60
cleared if interrupt is edge triggered
is set (
PMASK60
= 0...0).
or
IMASK60 PMASKN
: which automatically clears
RETIB
.
ISR
when the instruction
RETI
clear and
ILAT
set?
PMASK60
is embedded in
PMASK_R
set
PMASK60
have to be specified in
RETIB
ADSP-TS101 TigerSHARC Processor
Hardware Reference
bits set, if
PMASK
, that is,
set, the ISR should:
PMASK60