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Table 10-2. General Pin Descriptions (Cont'd)
Signal
TDI
TDO
TMR0E
TMS
TRST
V
DD
V
DD_A
V
DD_IO
V
REF
V
SS
V
SS_A
WRH
WRL
!
All pins are sampled by a clock, either a system clock (SCLK) or
core clock (CCLK).
!
No keeper latches exist on TigerSHARC processor.
Strap Pin Function Descriptions
Some pins have alternate functions at reset. Strap options set Tiger-
SHARC processor operating modes. During reset, the TigerSHARC
processor samples the strap option pins. Strap pins have an approximately
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Type
Description
I
Test Data Input (JTAG)
O/T
Test Data Output (JTAG)
O
Timer 0 expires
I
Test Mode Select (JTAG).
I/A
Test Reset (JTAG)
P
VDD pins for internal logic
P
VDD pins for analog circuits. Pay critical attention to bypassing
this supply.
P
VDD pins for I/O buffers
I
Reference voltage defines the trip point for all input buffers,
except
RESET
,
, and
TDI
TMS
G
Ground pins
G
Ground pins for analog circuits
I/O/T
Write High
I/O/T
Write Low
,
,
,
IRQ3–0
DMAR3–0
ID2–0
.
TRST
System Design
,
,
,
CONTROLIMP2–0
TCK
10-7
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