Bus Interface I/O Pins; Processor Microarchitecture - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

• Protocol supporting wait cycles inserted by the target slave, using
the
ACK
• EPROM and FLASH interface: 8-bit data bus with a fixed number
of wait cycles, read or write
• Host interface
• SDRAM interface: no wait cycles required
• Support for slow I/O devices
• Glueless multiprocessing with other TigerSHARC processors,
based on distributed bus arbitration
• Support of DMA transactions for external I/O devices through
handshake mode
• Support for flyby between external memory and I/O in DMA

Bus Interface I/O Pins

Table 5-1 on page 5-4 lists the bus interface I/O pins. See Table 6-1 on
page 6-7 for those I/O pins associated with SDRAM and Table 5-3 on
page 5-38 for those associated with multiprocessing. Figure 6-3 on
page 6-12 and Figure 6-2 on page 6-11 show the External Port Data
Alignment.

Processor Microarchitecture

The TigerSHARC processor functions differently depending on the type
of system in which it is used. It can perform as a single processor or in a
multiprocessing system on a common external bus (as shown in Figure 5-1
on page 5-6). There may be a host (or host interface) in the system as well,
ADSP-TS101 TigerSHARC Processor
Hardware Reference
pin
Cluster Bus
5-3