Performance Monitors - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Performance Monitors

The trace buffer is an eight register list that stores a history of the last four
to eight branches taken by the program sequencer, allowing the user to
fully recreate the path the program took for the last eight branches.
The branches are written into the eight Trace Buffer registers in a circular
manner. The first is written into
until . The ninth branch is written back into
TRCB7
order to ascertain the last register, the user must refer to the Trace Buffer
pointer register, which points to the last written entry.
The trace buffer always holds the PC of the branch instruction line. In
case of a computed branch, it also stores the target PC of the branch on
the next entry. To distinguish between the jump PC and the target PC,
the should be used. Every bit in the
TRCBMASK
the corresponding
the jump instruction line. If set, the
jump.
Performance Monitors
The performance monitors are targeted to optimize the functioning of a
working application. The monitors provide indications of how many
times an event occurs during a specific run. These monitors are con-
structed of three registers—cycle counter, performance monitor mask, and
performance monitor counter. The cycle counter and performance moni-
tor should be initialized to zero by the user before a specific run. The ratio
between the total count and the performance monitor counter gives the
required indication.
When the performance monitor counter expires, it issues an exception.
9-10
TRCB0
register. If it is cleared, the
TRCBi
ADSP-TS101 TigerSHARC Processor
, the next into
TRCB1
TRCB0
TRCBMASK
TRCBi
holds the target PC of the
TRCBi
Hardware Reference
, and so on
, and so on. In
is associated with
holds the PC of