Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 226

SDRAM Controller Commands
Bus Width = 64
For the sequence in Figure 6-7, the following is true:
• latency = 2
CAS
• Bus width = 64
SCLK
SDCKE
MSSD
RAS
CAS
SDWE
RA1
A11-0
DATA63-0
DQ M
Figure 6-7. Bus Width = 64
(Burst Read Followed by Burst Read in the Same Page)
6-36
CA1 CB1
QUAD-WORD
DA1
ADSP-TS101 TigerSHARC Processor
QUAD-WORD
DA2 DB1 DB2
Hardware Reference