Table of Contents
Advertisement
Debug Resources
Table 9-2. WPiCTL Register Bit Descriptions
Bits
Bit
1–0
OPMODE
7–2
BM
8
R
9
W
11–10
EXTYPE
9-6
Description
Operation Mode
Determines the type of watchpoint operation.
00 – Watchpoint disabled and not in use.
01 – Watchpoint is used to compare a single address
(breakpoint). In this case, the low Watchpoint Address
register defines the target address.
10 – Watchpoint register is used to define an address range. The
two Watchpoint registers define the range of search.
11 – Determines address ranges beyond the usual range. The
search is for transactions inside the memory block, but outside of
the range (addresses lower than the lowest
address defined by the Watchpoint register, or higher
than the highest address defined by the Watchpoint
register).
Bus Master Selections
Any bus master or any combination of bus masters can be selected
to trigger the event. Every master has one bit, when if set, the
watchpoint monitors the transactions initiated by this module.
The transactions of the core (sequencer, J-IALU, and K-IALU)
are referred to only when initiating instruction executions have
completed, and only if these are not aborted. For more informa-
tion, see "Watchpoint Control – WP0CTL, WP1CTL and
WP2CTL" on page 2-25.
Read
If set, read to memory transactions are monitored.
Write
If set, write to memory transactions are monitored.
Exception Type
Determines the procedure following count experiment.
00 – No exception. This option is used to get an indication of the
output of the
pin.
EMU
01 – Regular software exception is performed.
10 – Emulation trap is executed.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Advertisement
Table of Contents
