Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 299

Table 7-14. Internal/External Memory to Link TCB
Transmitter TCB Configuration
Register Field
DI
DX
DY
DP TY
DP PR
DP 2DDMA
DP LEN
DP INT
DP DRQ
DP CHEN
DP CHTG
DP CHPT
The DMA initiates a transfer by requesting the internal bus, and data is
transferred from the link port that requested the DMA services to the
receiver link port.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Description
Internal/external memory address
Number of words to transfer and address modifier. The
to X dimension data when the
Number of Y dimension words to transfer and address modifier when the
bit is set in the
2DDMA DP
Internal/external memory
Channel priority
1 – Increases the channel priority – internal/cluster bus DMA request
priority is high.
Sets the two-dimensional DMA mode
1 – Enables two-dimensional DMA mode;
(See "Two-Dimensional DMA" on page 7-45.)
Always set to quad-word.
Sets interrupt
1 – Interrupts the core once the complete block is transferred.
Don't care (set in hardware)
Sets chaining
1 – Enables chaining.
Defines register to be loaded; may be any link channel.
TCB
Chaining pointer – relevant when chaining is enabled.
Direct Memory Access
bit is set in the
2DDMA
register; otherwise irrelevant.
register becomes relevant.
DY
register also refers
DX
register.
DP
7-65