Dma Channel Prioritization - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

DMA Controller Operations
When DMA is from internal/external memory to the external/internal
memory, two
TCB
address generation; the second is used to generate 32-bit addresses to be
driven out of the external port. If the two-dimensional DMA option is
enabled, the count value equals the
register count. It is important to stress that different count values
DY Y
cause the DMA to cease once the transfer of the shorter block is complete.
"Transfer Control Block (TCB) Registers" on page 7-15 lists the
isters for each DMA channel. The
hardware reset, except for the boot channel
"DMA Operation on Boot" on page 10-32.

DMA Channel Prioritization

The overall DMA prioritization is defined by internal bus priority as well
as DMA channels priority.
Internal Memory Bus Priority
DMA arbitration resolves priority conflicts between DMA channels.
Internal memory buses have different arbitration levels that define priority
between internal memory bus masters. The internal memory bus priority
is described in "Processor Microarchitecture" on page 5-3.
DMA Channel Priority
Since more than one DMA channel may have a request active in a particu-
lar cycle, a prioritization scheme is used to select the channel to service.
The TigerSHARC processor always uses a fixed prioritization between I/O
groups. Table 7-3 on page 7-38 lists the DMA groups in descending order
of priority.
7-36
registers are used. One is used for the internal DMA
TCB
TCB
ADSP-TS101 TigerSHARC Processor
register count times the
DX X
registers are disabled following a
. For more information, see
TCB
Hardware Reference
TCB
reg-
TCB