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Table 9-2. WPiCTL Register Bit Descriptions (Cont'd)
Bits
Bit
12
SSTP/WPOR/WPAND 1
15–13
31–16
COUNTER
1 When
and
WPOR
2
can be used to detect accesses that cross memory block boundaries. Split the range in the
WPOR
memory block and each subrange can be detected by a different watchpoint set.
Watchpoint Operation
The following information must be programmed into the Watchpoint
registers before a search can begin:
• Address or address range
• Master initiating the transaction
• Count
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Description
Watchpoint register OR and AND bits
In
and
WP1CTL
. When one of these is set, the three watchpoint sets work
WPAND
together. If the
mented every time one of the watchpoints finds a match.
If the
WPAND
every time all the watchpoints find a match in the same cycle.
Note this bit is meaningless in
rides the setup of the watchpoint.
Reserved
Watchpoint Counter Initialization
Defines how many times the event should be triggered before it
causes an exception or emulation trap. It can be set between 1 and
64K-1. Note zero may not be
programmed.
are set, all three watchpoints must be initialized and enabled.
WPAND
Debug Functionality
Bit12 of the control register is
WP2CTL
bit is set in
WPOR
WP1CTL
bit is set in
, the counter is decremented
WP2CTL
WP0CTL
and
WPOR
, the counter is decre-
2
—in
this bit over-
WP0CTL,
9-7
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