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Checksum = B0 + B1 + ... + B15 + C0 + C1 + ... + C13
where B0, B1, and so on are byte1, byte2 ...
C0 is the Carry_out from B0 + B1,
C1 is the Carry_out from B0 + B1 + B2 + C0,
and so on
C15 (the Carry_out from B0 + B1 + ... + B15 + C0 + C1 + ... +
C13) is not added to the checksum
• Time out
If
LxCLKIN
error has occurred. The
hardware interrupt is issued. If less than 16 bytes are received and
LxCLKIN
does not detect a timeout error. The next quad-word received over-
writes the data in the receive buffer.
Control Register (LCTLx)
The control register programs every link port and contains control bits
unique to each one. There are four control registers—one for each link
port. The register is read/write.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
is sampled low for a period of 256 cycles, a timeout
RER1
remains high for more than four
bit is set in the
LSTATx
LxCLK
Link Ports
register and a
cycles, the receiver
8-19
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