General High Speed Clock Distribution Issues - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Clock Description and Jitter
buffers must be in the same IC and must be specified for low jitter and
low skew with respect to each other. The jitter and skew should be as small
as possible because it subtracts from the margin on most specifications.
"
Never share a clock buffer IC with a signal of a different clock fre-
quency. This introduces excessive jitter.
CLOCK
Figure 10-3. System Clock Distribution

General High Speed Clock Distribution Issues

For additional information on handling jitter, refer to ADSP-TS101 Tig-
erSHARC Embedded Processor Data Sheet.
10-16
FANOUT CLOCK BUFFER
R
T
TRANSMISSION LINE
R
T
TRANSMISSION LINE
R
T
TRANSMISSION LINE
A SEPARATE BUFFER AND
TRANSMISSION LINE IS NEEDED
FOR EACH PROCESSOR.
ADSP-TS101 TigerSHARC Processor
ADSP-TS101
ADSP-TS101
ADSP-TS101
Hardware Reference