Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 323

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Figure 8-12. LCTLx (Lower) Register Bit Descriptions
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Reserved
VERE Verification Enable
SPD Transfer Speed
LTEN Transmit Enable
PSIZE Packet Size
TTOE Transmit Time Out check Enable
CERE Connectivity Error check Enable
LREN Receive/Enable
RTOE Receive Time Out check Enable
Reserved
Link Ports
8-21