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LCTLx Register Bit Descriptions
8-22
LCTLx see link port
Len Setup 7-28
Level or Edge Interrupts 4-3
level sensitive 4-3–4-4, 4-7, 4-8,
4-12, 10-8
Link Architecture 8-2
Link Boot
Internal Memory TCB 10-36
link boot 3-1, 8-7
Link I/O Pins 8-2, 8-3
link interrupt 2-20, 4-5, 4-12
Link Interrupts 4-5
link port 1-3, 1-7, 1-23, 3-4, 7-32,
7-63–7-65, 8-1, 10-8
architecture 8-2–8-8
DMA 8-5–8-7
error detection 8-17–8-19
I/O pins 8-2
interrupt 8-7
link
port
control
(LCTLx) 8-19–8-23
link port protocol 8-8–8-15
links registers 2-47, 2-48
LSTAT Link Status register
8-6, 8-17, 8-18, 8-19
transmission delays 8-15–8-17
transmitting and receiving data
8-4–8-6
Link Port Boot 10-24
link port boot 10-24
Link Port Communication Proto-
col 8-8
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Link Port Control and Status Reg-
ister 2-47
Link Port Control and Status
Register 2-47
Link Port DMA Control 7-32
Link Port Receive and Transmit
Buffers 2-48
Link Port Receive DMA Register
2-45
Link Port Receive DMA Register
2-45
Link Port Register 8-5, 8-6
Link Port to Internal/External
Memory 7-63
Link Port Transmit DMA Register
2-45
Link Port Transmit DMA Register
2-45
Link Ports 1-23, 8-1
Link Ports DMA 7-63
Link Ports DMA Transfer Types
register
7-63
Link Registers 2-47
Link to Internal/External Memory
TCB 7-64
Link to Link TCB 7-66
Link Transfers 7-9
load 1-12
local clock see LCLK
Low Power Mode 3-6
low power mode 3-6
Low Word SDRAM Data Mask
(LDQM) 6-7, 6-9
low-power mode 3-8
INDEX
xi
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