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SDRAM Programming
In the
register, set the parameter bits as follows.
SDRCON
• Enable the SDRAM.
• Select the
• Set the SDRAM buffering option (pipeline depth)
• Select the SDRAM page size (page boundary)
• Select the refresh counter value (refresh rate)
• Set the Precharge to
• Set the
• Select the SDRAM power up mode (Init sequence)
SDRAM Enable
Bit0 should be set if there is an SDRAM in the system, otherwise it should
be cleared. Any access to SDRAM while this bit is cleared causes a hard-
ware error interrupt.
Selecting the CAS Latency Value (CL)
The
latency value defines the delay, in number of system clock cycles
CAS
(
), between the time that the SDRAM detects the read command and
SCLK
the time that it provides the data at its output pins. This parameter facili-
tates matching the SDRAM operation with the processor's ability to latch
the data output.
latency does not apply to write cycles.
CAS
The
Bits2–1 in the
CL
follows.
00 = 1 cycle latency
6-22
latency value (CL)
CAS
delay (t
RAS
to Precharge delay (t
RAS
register select the
SDRCON
)
RP
)
RAS
latency value as
CAS
ADSP-TS101 TigerSHARC Processor
Hardware Reference
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