Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 286

External Port DMA
Table 7-4. Dual TCB Channel – External Memory TCB
Transmitter TCB Configuration
Register Field
DI
DX
DY
DP TY
DP PR
DP 2DDMA
DP LEN
DP INT
DP DRQ
DP CHEN
DP CHTG
DP CHPT
7-52
Description
External memory address
Number of words to transfer and address modifier. The
refers to X dimension data when the
Number of Y dimension words to transfer and address modifier when the
bit is set in the
2DDMA DP
External memory
Sets the channel priority
1 – Increases the channel priority – the cluster bus transaction is
signaled as a (Priority Access) transaction
DPA
Sets the two-dimensional mode
1 – Enables the two-dimensional mode –
DMA mode. (See "Two-Dimensional DMA" on page 7-45.)
Can be word, double word or quad-word. Note the lowest internal bus
utilization is achieved with quad-words.
Sets interrupt
1 – Interrupts the core after the complete block is transferred. (Enabled
if set in either the source or destination
Sets transfer mode
1 – Transfers each data item per
the source or destination
Sets chaining mode
1 – Enables chaining.
Defines the register to be loaded; must be the same channel.
TCB
Chaining pointer – relevant when chaining is enabled.
ADSP-TS101 TigerSHARC Processor
bit is set in the
2DDMA
register; otherwise irrelevant.
register becomes relevant
DY
register.)
TCBxDP
assertion. (Enabled if set in either
DMARx
register.)
TCBxDP
Hardware Reference
register also
DX
register.
DP