Transmitting And Receiving Data - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Link Architecture
between the
LxDAT
can be regular buffers. The delays on all
exactly matched. Buffers must be disabled by
three-stated by the TigerSHARC processor.)
LxCLKIN
LxCLKOUT
LxDAT
LxDIR
LINK PORT 0
Figure 8-3. Buffered Link Configuration Using LxDIR

Transmitting and Receiving Data

Data is transferred by writing to the
register. Core driven transfer is performed by the core writing
LBUFRx
quad-word data to the
data from the
LBUFRx
two DMA channels per link port, one for transmit and one for receive.
The link port DMA requires a Transfer Control Block (
transmit or receive, and only quad-word transfers are allowed. DMA
chaining is supported.
All the data written to the
ter when it is empty, and then transmitted. After the data is copied to the
shift register, new data can be written to the
8-4
pins that are controlled by
8
LBUFTx
register, and the core reading quad-word
LBUFTx
register. DMA driven transfer is performed through
register is first copied to the shift regis-
LBUFTx
ADSP-TS101 TigerSHARC Processor
. The
LxDIR LxCLK
and signals must be
LxCLK LxDAT
(the output
RESET
LxCLKIN
LxCLKOUT
LxDAT
LxDIR
register and reading from the
TCB
register.
LBUFTx
Hardware Reference
buffers
is
LxDIR
LINK PORT 1
) for either