Eprom Interface - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

BASIC
SCLK
ADDR
DATA
MS1-0/ H
RD
Figure 5-14. Slow Protocol Read With Wait Cycles

EPROM Interface

The TigerSHARC processor can be configured during reset to boot from
an external 8-bit EPROM. In this case, the program is loaded from the
EPROM into internal memory by an automatic process as part of the reset
sequence. The TigerSHARC processor uses a specific DMA channel to
load the program. The TigerSHARC processor bus interface packs bytes
to 32-bit instructions. EPROM may also be accessed during normal work
via DMA. The boot EPROM cannot be accessed by the core. The
EPROM is a byte address space and is not part of the TigerSHARC pro-
cessor memory space. It is limited to 16M bytes (maximum address is
,
0xFF FFFF ADDR31–24
Bits7–0.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
INT WAIT
CYCLES
= 0). The data is driven on the regular data bus
Cluster Bus
DATA
5-31