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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 2-9. SYSTAT/SYSTATCL (Lower) Register Bit Descriptions
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Memory and Register Map
PROCESSOR ID
Indicates the processor ID in the system
Reserved
CURRENT BUS MASTER
Indicates the current bus master ID
HOST MASTER
Indicates if the bus master is the host
MULT CLOCK Clock multiplication
000 – CCLK = 2xLCLK
001 – CCLK = 2.5xLCLK
010 – CCLK = 3xLCLK
011 – CCLK = 3.5xLCLK
100 – CCLK = 4xLCLK
101 – CCLK = 5xLCLK
110 – CCLK = 6xLCLK
111 – Reserved
REAL FREQ Write transactions
0 – SCLK<50 MHz
1 – SCLK>50 MHz
BOOT MODE When clear, boot is performed
by EPROM; otherwise by another boot
mechanism
MRS COMPLETE SDRAM MRS (Mode Regis-
ter Set) sequence is completed (in ID=0
only)–indicates that it is legal to access
SDRAM
BUSLOCK ACTIVE Bus lock bit is set and the
bus is held by the TigerSHARC processor
Reserved
2-33
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