Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 230

SDRAM Controller Commands
Bus Width = 64
For the sequence in Figure 6-10, the following is true:
• latency = 2
CAS
• Bus width = 64
SCLK
SDCKE
MSSD
RAS
CAS
SDWE
RA1
A11-0
DATA63-0
DQM
Figure 6-9. Bus Width = 64
(Burst Write Followed by Burst Write in the Same Page)
6-40
CA1 CB1
QUAD-WORD QUAD-WORD
DA1 DA2 DB1
ADSP-TS101 TigerSHARC Processor
DB2
Hardware Reference