Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 127

The following algorithm describes the interrupt service routine.
!
In ISR the first instruction must not be
1. The interrupt vector in Interrupt Vector Table (IVT) is used as the
next fetch address and the ISR's first instruction is pushed into the
pipeline. If the interrupt is a hardware interrupt, normal execution
continues until the first interrupt routine instruction reaches pipe-
line stage EX2. Otherwise, for software exceptions that are not
hardware interrupts, all the normal flow instructions that are in the
pipeline are aborted. While an interrupt is in the pipeline, all the
hardware interrupts are disabled, although this is not reflected in
the mask registers (
If the exception is disabled, the
and the exception is ignored. The reason is that the instruction line
that caused the exception is lost.
2. Instructions in the pipe are executed.
3. Before the first instruction in the interrupt routine reaches EX2,
the global enable interrupts (
the bit was cleared since the interrupt was generated by an instruc-
tion already in the pipeline, then all the instructions in the pipeline
are aborted and the TigerSHARC processor begins fetching from
the normal flow (as if there were no interrupt).
!
If instructions are ordered in a specific way, it is possible to enter
an ISR immediately after it's bit is cleared in the
While in the ISR,
any way.
4. The return PC (which points to the instruction that would have
been executed had the interrupt not occurred) is saved in the
appropriate register—
software interrupt, and
ADSP-TS101 TigerSHARC Processor
Hardware Reference
or ).
PMASK IMASK
ILAT
IMASK60
bit = 0, which does not affect operation in
IMASK
for a hardware interrupt,
RETI
for an emulation debug.
DBGE
or .
RDS RTI
bit for the exception is not set
, ) are rechecked. If
PMASK60
IMASK
RETS
Interrupts
register.
for a
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