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ADDRESS
CYCLE
SCLK
ADDR,
RD / WRx
DATA
ACK
Figure 5-5. Basic Pipelined Transaction
The pipeline depth is configured according to the slave and the transac-
tion type (read or write). For write transactions, the pipeline depth is
always 1. For read from another TigerSHARC processor in multiprocess-
ing systems, the pipeline depth is always 4. When reading from external
memory banks or host memory space, the pipeline depth is user-program-
mable and can be up to four cycles. Pipeline depth can be selected
individually for each of the banks (bank0, bank1, and host) in the
register after reset.
Single transactions take a different number of cycles according to transac-
tion size and external bus width:
• Single transactions: one cycle
• Long transactions on 64-bit bus: one cycle
• Long transactions on 32-bit bus: two cycles
ADSP-TS101 TigerSHARC Processor
Hardware Reference
DATA
CYCLE
PIPELINE DEPTH = 2
Cluster Bus
SYSCON
5-17
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