DCNT Register ................................................................ 7-26
DCNTST Register ............................................................ 7-28
DCNTCL Register ............................................................ 7-28
DMA Control Register Restrictions ....................................... 7-28
Operand Length Setup (Len) ............................................. 7-28
Count (XCOUNT and YCOUNT) ................................... 7-28
Type Setup - Links Transmit (Channels 4 to 7) ................. 7-29
Type Setup - Links Receive (Channels 8 to 11) .................. 7-29
Type Setup - EP (Channels 0 to 3) .................................... 7-30
Type Setup - AutoDMA (Channels 12, 13) ....................... 7-30
DMA Request ................................................................... 7-30
Alignments ....................................................................... 7-30
Address Range .................................................................. 7-31
Link Port DMA Control ........................................................ 7-32
External Port DMA Control .................................................. 7-32
DMA Transfers ...................................................................... 7-33
Internal Memory Buses ..................................................... 7-33
DMA Channels ................................................................. 7-34
DMA Memory Accesses ......................................................... 7-34
Internal Memory Bus Priority ............................................ 7-36
DMA Channel Priority ..................................................... 7-36
ADSP-TS101 TigerSHARC Processor
Hardware Reference
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