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DMA Controller Operations
This is under the assumption that all channels do not set the priority bit in
, or that all channels do set it. If one or more of the channels is set to
TCB
high priority, it is selected at a separate arbitration level. In this case there
is one round robin for the higher priority channels, and another round
robin for the lower priority channels. For example, if after reset
channel 2, the
• channel 2 (priority bit set)
• channel 3 (highest)
• channel 1
• channel 0 (lowest)
If channel 1 requests and the request is granted, the priority scheme is:
• channel 2 (priority bit set)
• channel 1 (highest)
• channel 0
• channel 3 (lowest)
If during the operation of channel 1, channel 2 makes a request, it is
granted and the channel 1 operation is interrupted. When it completes
executing its transactions, the scheme of the lower priority channels is
unchanged, and channel 1 wins the arbitration and continues its transfers.
If there is more than one channel with priority bit set, the arbitration
between these channels is in a similar round robin manner.
7-40
priority bit is set, the priority is:
TCB
ADSP-TS101 TigerSHARC Processor
Hardware Reference
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