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Timers
The TigerSHARC processor has two general-purpose 64-bit timers—
Timer 0 and Timer 1. The timers are free-running counters that are
loaded with an initial value and give an indication when expiring. The
indication is normally an interrupt, but could also be an external pin for
Timer 0.
Timer Registers
Each timer is composed of two long registers. One register is the initial
value (
TMRINxx
register is read/write and the
is read, the point in time at which it is read is uncertain. Conse-
TIMERxx
quently, results may vary.
Like all the sequencer registers, the timer registers can be accessed only by
a single-word access.
Two bits in the sequencer control register enable the timer count—
for Timer 0 and
Timer Operations
The timers are initialized to idle status after reset (achieved by clearing the
bits in
TMRiRN
the
bit. When this bit is set, the value in
TMRiRN
timer registers, and these start counting down, one count every internal
clock cycle.
Whenever the timer count reaches zero, the timer issues the two timer
expire interrupts (high and low priority), reinitializes the counter to the
initial value, and starts running again. If the timer is active (
ADSP-TS101 TigerSHARC Processor
Hardware Reference
) and the other is the running value (
TIMERxx
for Timer 1.
TMR1RN
). To set the timers to run, the application has to set
SQCTL
TIMERxx
is read-only. When the value of
TMRINxx
Core Controls
). The
TMRINxx
TMR0RN
is copied to the
bit is
TMRIRN
3-9
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