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Table 9-5. JTAG Port Access Instruction Decode
If IR4–0 Value is...
00000
10000
01000
10100
01110
11110
10001
01001
11001
00101
10101
01101
11101
00011
10011
01011
00100
01100
11111
When registers are scanned out of the device, the LSB is the first bit to go
out of the TigerSHARC processor.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Corresponding Instruction is...
EXTEST
Sample/Preload
EMUIR
EMUDAT
IDCODE
SAMPLEPC
EMUTRAP
WP0CS
WP0L
WP0H
WP1CS
WP1L
WP1H
WP2CS
WP2L
WP2H
EMUCTL
EMUSTAT
BYPASS
Debug Functionality
To...
Execute
EXTEST
Execute sample and preload
Scan in
register
EMUIR
Scan
register
EMUDAT
Scan ID code register
Sample PC from which the Tiger-
SHARC processor is running
Execute an emulation trap
Scan out
status, and scan in
WP0
control
WP0
Scan
low
WP0
Scan
high
WP0
Scan out
status, and scan in
WP1
control
WP1
Scan
low
WP1
Scan
high
WP1
Scan out
status, and scan in
WP2
control
WP2
Scan
low
WP2
Scan
high
WP2
Scan
register
EMUCTL
Scan
register
EMUSTAT
Bypass
9-15
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