If the
pin is sampled low during reset, the boot mode is EPROM
BMS
boot.
• In order to boot from a single EPROM, you must connect all
pins to the EPROM CS pin on the EPROM. The
only driven by the TigerSHARC processor bus master. This allows
wire-OR'ing of multiple
EPROM.
• The EPROM loader kernel accepts multiple
the
field in
ID
The TigerSHARC processor with the lowest ID number is respon-
sible for initializing any external data that may be present in the
system.
An example system that uses this "processors-take-turns" technique
appears in Figure 10-5. When multiple DSPs boot from one EPROM, the
DSPs can boot either identical code or different code from the EPROM.
If the processors load different code, a jump table (based on processor ID)
can be used to select the code for each processor.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
signals for a single common boot
BMS
to determine which area of EPROM to read.
SYSTAT
System Design
BMS
output is
BMS
files and reads
.DXE
10-27
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