Data Alignment Buffer; Register Access Features; Register Space - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Data Alignment Buffer

Normally load instructions must be aligned to their data size so that
quad-words are loaded from a quad-aligned address. But some applica-
tions need to access non-aligned quad-words in memory. This can be done
by using the Data Alignment Buffer (DAB) instructions. Failure to use a
DAB instruction in accessing a non-aligned word results in an error.
The DAB is a quad-word FIFO in which the load from memory is aligned,
but the transfer to the processing elements register file is non-aligned. Part
of the data comes from a previous load from memory, and part comes
from the current load from memory. Thus at the start of each new DAB
access, the application must issue two consecutive accesses. The first is a
dummy access to clear the DAB of old data, the second access delivers
valid data. This is discussed on page 6-23 of the ADSP-TS101 Tiger-
SHARC Processor Programming Reference.

Register Access Features

Registers can be accessed in two ways—either by the core with a register
access instruction, or as a memory-mapped register by a different Tiger-
SHARC processor or Host that acts as a master. For example, two fields in
the memory mapped address, Ureg group and Ureg, can be used to access
the register via a register access instruction.

Register Space

The register space is composed of 64 register groups with up to 32 regis-
ters in each group. Register groups are defined in the range 0x3F–0 (63–
0), where groups 0x1F–0 are accessible by all transfer instructions (load
immediate, move register, load and store), and groups 0x3F–0x20 are
accessible only by move register instructions and direct accesses of other
masters.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Memory and Register Map
2-9