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Booting
2. Those first 256 instructions, called the loader kernel, automatically
execute and perform additional DMAs to load the application exe-
cutable code and data into internal and/or external memory.
3. Finally, the loader kernel overwrites itself with the application's
first 256 words.
No Boot Mode
The TigerSHARC processor begins execution from an address specified in
the vector table for each of the IRQs, depending on which
Booting a Single TigerSHARC Processor
The TigerSHARC processor supports booting from:
• EPROM/flash device – This is a master mode boot
• A host, such as another TigerSHARC processor or host processor –
This is a slave mode boot
• Any link port – This is a SLAVE Mode Boot
EPROM/Flash Device Boot
The EPROM boot is selected as default. The
option for the selection—if the
mode is EPROM boot.
After reset in EPROM boot, DMA channel 0 is automatically configured
to perform a 256-word block transfer from an 8-bit external boot
EPROM, starting at address 0 to internal memory, locations 0x00-0xFF.
The DMA channel 0 interrupt vector is initialized to internal memory
address 0x0. An interrupt occurs at the completion of the DMA channel 0
transfer and the TigerSHARC processor starts executing the boot loader
kernel at internal memory location 0x0.
10-20
pin is used as the strap
BMS
pin is sampled low during reset, the
BMS
ADSP-TS101 TigerSHARC Processor
is asserted.
IRQ
Hardware Reference
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