Exceptions - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

If the system supports nested interrupts, the state of the machine is saved
in memory at the beginning of the interrupt routine. The full state should
be restored in the original registers before the return. See "Interrupt Han-
dling" on page 4-19.
The instruction clears the highest set bit in
RTI
clears the global interrupt enable (
exception or emulation exception. The instruction then jumps to the
address pointed by the value in the
interrupts.
Interrupt routine restrictions:
• An interrupt routine may not refer to the
the first instruction line.
• An interrupt routine may not use the
on the first instruction line.

Exceptions

Exceptions are software interrupts—interrupts that are caused by code
being executed. Figure 4-2 illustrates what transpires when a software
interrupt is introduced. If the exception is enabled:
•
PMASK62
case of an emulation exception.
• The sequencer starts fetching from the address pointed to by the
register in case of an exception, or from the
IVSW
case of an emulation exception.
• PC is stored in
case of an emulation exception.
• Instructions are flushed from the pipeline.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
is set in case of a regular exception, or
in case of an exception, or in
RETS
PMASK
) if it is not an
PMASK60
register and re-enables the
RETI
RETI
,
RTI RETI
Interrupts
register. It also
from an
RTI
or registers on
RETS
, or instructions
RDS
is set in
PMASK63
register in
EMUIR
register in
DBGE
4-23