Table of Contents
Advertisement
5 CLUSTER BUS
The TigerSHARC processor can be used as a single processor or as one
element in a multiprocessor system. The processor can act as a standalone
TigerSHARC processor or system, or it can be controlled by a host com-
puter (for example, the TigerSHARC processor system can be an add-in
board on a PC). The system architecture is flexible, and can be imple-
mented according to the application requirements. The software "hooks"
for the different options lie within the TigerSHARC processor. This chap-
ter focuses on the external bus interface of the TigerSHARC processor,
which includes the bus arbitration logic and the external address, data,
and control buses.
The fastest protocol is the pipelined protocol. The TigerSHARC proces-
sor uses this protocol to interface with other TigerSHARC processors. The
TigerSHARC processor can also use this protocol to interface with host
and intelligent memory systems. The protocol has a peak performance of
one data transfer every clock cycle and can sustain a throughput close to
this peak performance because there is no restriction of address range for
continuous flow in full throughput.
Another fast protocol is the SDRAM protocol. This protocol is defined by
industry-standard SDRAM chips. The TigerSHARC processor has an
on-chip SDRAM controller that drives all the SDRAM control signals
(
,
,
,
RAS
CAS
DWE
the SDRAM chips. The SDRAM is useful for mass storage of the system,
since it is possible to build very large memory arrays. The peak data
throughput to the SDRAM is one data transfer every clock cycle. The
ADSP-TS101 TigerSHARC Processor
Hardware Reference
, and
) and handles the initialization and refresh of
CKE
DQM
5-1
Advertisement
Table of Contents
