Enabling And Disabling Chaining - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

DMA Controller Operations
• DMA sequence
A DMA sequence is defined as the sum of the DMA transfers for a
single channel, from the
count register decrements to zero.
Each has a chaining enable bit (
TCB
selected according to the value of the
address in the
memory address. (See "DPx Register" on page 7-18.)
For external/internal memory transfers, the chaining between the internal
and external channels must be coordinated. Both channels must have the
chaining enable bit set.

Enabling and Disabling Chaining

DMA transfers are initiated by writing a quad-word from memory to the
register (EP channels require both
TCBx
ing occurs if the chain enable bit is set, and the chain pointer is a valid
address.
The field in
CHPT
DMA sequence. This allows a DMA channel to have chaining disabled
(when the
CHEN
that loads the
CHPT
defines the
CHTG
I/O devices. While updating an active
the channel field in the
Interrupting Chaining
If the (interrupt enable) bit in
INT
occurs at the end of the current block transfer. Interrupts occur at the end
of the chain sequence, instead of after each transfer, when the
in the last chained
7-42
TCB
field of the same register selects the
CHPT
register
TCBx DP
bit is set to 0 in
TCBx
field with a target address, sets the
field. DMA chaining operations can be performed across
register.
DCNT
register.
TCB
registers initialization to when the
) in register
CHEN
field in
CHTG TCBx
registers to be loaded). Chain-
TCB
can be loaded at any time during the
register ) until some event occurs
DP
, it must be paused by writing to
TCB
register is high, an interrupt
TCBx DP
ADSP-TS101 TigerSHARC Processor
. The channel is
DP
register . The
DP
's internal
TCB
bit, and
CHEN
bit is set
INT
Hardware Reference