Wait Cycles - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

The illustrated sequence in Figure 5-8 assumes a different pipeline depth
and a bus width of 32.
SCLK
PIPE LEVEL 3
AA0 AA 1
ADDR
DATA
RD
BRST
ACK
Figure 5-8. Read Followed by Read From Different Slave

Wait Cycles

In regular transactions, if the slave is ready in time for the data cycle of the
targeted transactions, the slave asserts the
the slave is not ready, it deasserts the
keeps it deasserted until it can continue.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
PIPE
DEPTH
DIFF
AA2 AA3
QUAD-WORD
DA0 DA1
DATA SLAVE A
IDLE
AB0 AB1
DA2 DA3
signal in the data cycle. If
ACK
signal on the data cycle and
ACK
Cluster Bus
PIPE LEVEL 2
AB2 AB3
QUAD-WORD
D0 DB1 DB2
DATA SLAVE B
5-23