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The SDRAM is organized internally into two or four banks. The SDRAM
Bank Select pins determine which bank is being addressed. The SDRAM
has a programmable read latency parameter that must be initialized by the
application according to the type of device and the operating clock
frequency.
In order to meet the demanding SDRAM timing requirements, the Tiger-
SHARC processor allows the SDRAM address and controls to be
pipelined. The pipeline depth bit in the
purpose. When this bit is set, data in write accesses are delayed by one
cycle, allowing the address and controls to be externally latched and
optionally manipulated in one cycle (for example, selection between Dual
In-line Memory Modules (DIMMs) in the array). In pipelined read
accesses, data is sampled by the TigerSHARC processor one cycle later.
(
latency plus pipeline cycle are maximum four cycles.) (Refer to the
CAS
timing diagram in the ADSP-TS101 TigerSHARC Embedded Processor
Data Sheet.) Pipelining can be used when connecting several SDRAM
devices in parallel such that their collective load is too high to be driven by
the TigerSHARC processor.
SDRAM chips are available from different vendors. Each vendor has vari-
ations on timing requirements pertaining to
(t
) and
PRE
RAS
vendors and different speed grades, the
help the system designer meet the specific SDRAM timing requirements.
The bit fields are
"SDRCON (SDRAM Configuration) (DMA 0x180484)" on page 2-36
for more information regarding
The TigerSHARC processor programs the SDRAM to full-page bursts.
This allows other bus agents that have their own SDRAM controller, for
example, host, to perform full-page burst transactions. The TigerSHARC
processor itself operates in bursts of up to four data units. Whenever pos-
sible, however, it issues a new
enough to make the whole sequence look like a continuous burst.
6-2
to
command delays (t
ACT
latency,
CAS
PRE
SDRCON
CAS
register is used for this
SDRCON
to
ACT
PRE
). In order to support all major
RP
register is programmed to
SDRCON
to
delay, and
RAS
RAS
register definitions.
for the following transaction early
ADSP-TS101 TigerSHARC Processor
command delays
to
delay. See
PRE
Hardware Reference
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