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3. Host releases the system bus between broadcast writes if initializa-
tion of external memory by the TigerSHARC processor is
necessary.
4. Host polls DMA status register (
system in order to determine when the next broadcast write can
occur.
DSTAT
ually since reading from broadcast MMS is not allowed. Each
processor's
plete when that processor is ready to accept another normal-word
broadcast write. The host must wait until all processors are ready
before it can perform another broadcast write, otherwise date could
be lost.
5. Steps 2 - 4 repeat until boot process completes.
Memory Initialization During Boot
During a boot process, the loader kernel initializes variables. Zeroed arrays
are stored in compressed format and initialized, as required by ANSI C
standards. Even if they are not explicitly initialized, large variables can
potentially fill large amounts of space in object and executable files. To
prevent use of large amounts of space in these files and allow the creation
of non-initialized variables, use the
Linker Description File (LDF) to direct the linker to omit an output sec-
tion from the output file. For details on LDF and
VisualDSP++ Linker and Utilities Manual for TigerSHARC DSPs.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
polling must be performed for each processor individ-
register indicates a status of either Active or Com-
DSTAT
SHT_NOBITS
System Design
) of each processor in the
DSTAT
section header in the
SHT_NOBITS
, see the
10-31
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