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•
/
HDQM
LDQM
by the controller to mask write operations. See "Understanding
DQM Operation" on page 6-29.
•
SDRCON
SDRAM control and configuration parameters that support differ-
ent vendor's timing and power up sequence requirements.
• Mode Register. The SDRAM configuration register that contains
user-defined parameters corresponding to the processor
ister. After initial power up and before executing a read or write
command, the application must program the initialization
sequence in the
• Page Size. The size, in words, of the SDRAM page. The processor
supports 1024-, 512-, and 256-word page sizes. Page size is a pro-
grammable option in the
• Precharge Command. Precharges an active bank.
• Refresh Rate. Programmable value in the
clock supplied to the SDRAM can vary between 50 and 100 MHz.
The refresh rate enables applications to coordinate
the SDRAM's required refresh rate.
• Self-Refresh. The SDRAM internal timer initiates automatic
refresh cycles periodically, without external control input. This
command places the SDRAM device in a low power mode.
• t
. Active Command time. Required delay between issuing an
RAS
activate command and issuing a precharge command. A ven-
dor-specific value. This option is programmable in the
register.
6-4
Data I/O Mask Function. The
Register. An IOP register that contains programmable
register.
SDRCON
SDRCON
/
HDQM
register.
SDRCON
ADSP-TS101 TigerSHARC Processor
Hardware Reference
pins are used
LDQM
reg-
SDRCON
register. The
rate with
SCLK
SDRCON
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