Operation Modes - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Operation Modes

same output from the same clock buffer or the output from two different
buffers driven by the same initial clock source. Both inputs are
differential.
The is the cluster bus interface clock. The cluster bus signals are
SCLK
specified in the ADSP-TS101 TigerSHARC Embedded Processor Data Sheet
with respect to this clock.
The is the input clock to an Analog Phase Locked Loop (PLL) that
LCLK
generates the internal clock
internal bus, and so on.) use
is the frequency of
CCLK
input pins
LCLKRAT2—0
In a system that must work deterministically cycle-by-cycle, only an inte-
ger multiplication (2, 3, 4, 5, or 6) should be used when setting
LCLK
.
LCLKRAT
!
For more information on using clock ratios, see the ADSP-TS101
TigerSHARC Embedded Processor Data Sheet.
Operation Modes
The TigerSHARC processor can operate in one of three modes: emula-
tion, supervisor, or user. In each of these modes, all instructions are
executed normally. The current operating mode of the TigerSHARC pro-
cessor affects which components of the processor are active and can be
accessed, as well as which exceptions are taken, and how they are handled.
The modes are described from highest to lowest priority.
3-2
. All the internal descriptions (pipeline,
CCLK
as the reference clock. The frequency of
CCLK
multiplied by a constant value defined by the
LCLK
. The constant can be 2, 2.5, 3, 3.5, 4, 5, or 6.
ADSP-TS101 TigerSHARC Processor
Hardware Reference