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DSP Architecture
The processing core of the TigerSHARC reaches exceptionally high per-
formance through using these features:
• Computation pipeline
• Dual computation units
• Execution of up to four instructions per cycle
• Access of up to eight words per cycle from memory
The two computation units (compute blocks) perform up to 6 floating-
point or 24 fixed-point operations per cycle.
Each multiplier and ALU unit can execute four 16-bit fixed-point opera-
tions per cycle, using Single-Instruction, Multiple-Data (SIMD)
operation. This operation boosts performance of critical imaging and sig-
nal processing applications that use fixed-point data.
Compute Blocks
The TigerSHARC processor core contains two computation units called
compute blocks. Each compute block contains a register file and three inde-
pendent computation units—an ALU, a multiplier, and a shifter. For
meeting a wide variety of processing needs, the computation units process
data in several fixed- and floating-point formats listed here and shown in
Figure 1-5:
• Fixed-point format
These include 64-bit long-word, 32-bit normal word, 16-bit short
word, and 8-bit byte word. For short word fixed-point arithmetic,
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ADSP-TS101 TigerSHARC Processor
Hardware Reference
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