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DMA Controller Features
• External to internal memory transfers
Transmitter DMA
memory address, the address increment, the number of transfers,
and control bits. Receiver DMA
the internal memory address, the address increment, the number of
transfer, and control bits.
Once setup programming is complete, DMA transfers start automatically
and either continue until the entire block is transferred, or until one trans-
action after each
the instructions to be followed.
• External device and external memory transfers
An additional DMA capability allows the TigerSHARC processor
to support data transfers between an external device and external
memory (flyby transactions). This transfer does not interfere with
internal TigerSHARC processor operations.
An external I/O device, unlike memory, gives an indication of
readiness for data transfer. A source device is ready if it has data to
write. A receiver is ready when it has space in its write buffer.
There are two techniques available for synchronizing these devices
with the TigerSHARC processor DMA channels:
• The source or receiver can assert a DMA Request input
(
DMA, requests are accumulated in the DMA and a transac-
tion is issued on the corresponding channel per DMA
request. Up to 15 requests may be accumulated.
• A source that can be a master on the cluster bus can write to
an AutoDMA register. After data is written to the
AutoDMA register, the AutoDMA channel transfers the
data according to its initialization.
7-8
registers are programmed with the external
TCB
pulse. The programming of the
DMARx
) every time it is ready to transfer new data. The
DMARx
registers are programmed with
TCB
ADSP-TS101 TigerSHARC Processor
Hardware Reference
s determines
TCB
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