Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 91

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 31-16 continued on Figure 2-12
Figure 2-13. SDRCON (Lower) Register Bit Descriptions
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Memory and Register Map
SDRAM ENABLE When set, determines an
SDRAM is in the system.
CAS LATENCY Determines the CAS latency
00 – One cycle
01 – Two cycles
PIPE DEPTH When set, level is 1, else zero.
PAGE BOUNDARY Indicates address where
burst is to be broken
00 – 256 word
10 – 1K
Reserved
REFRESH RATE Determines the refresh rate
in cycles
SCLK
00 – Once every 600 cycles
01 – Once every 900 cycles
10 – Once every 1200 cycles
11 – Once every 2400 cycles
PRC TO RAS DELAY Determines the delay
between the precharge and the next
00 – Two cycles
10 – Four cycles
RAS TO PRC DELAY Determines the delay
between the RAS and the next precharge
000 – Two cycles
001 – Three cycles
010 – Four cycles
011 – Five cycles
INIT SEQUENCE Initialization sequence
1 – MRS cycle follows refresh in the
SDRAM initialization sequence
0 – MRS precedes refresh
Reserved
10 – Three cycles
11 – Reserved
01 – 512 word
11 – Reserved
RAS
01 – Three cycles
11 –Five cycles
100 – Six cycles
101 – Seven cycles
110 – Eight cycles
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