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Memory Access Features
The external multiprocessor address is divided into two fields, as illus-
trated in Table 2-3 on page 2-6.
Table 2-3. External Multiprocessor Space
Bits
Name or Value Definition
ADDR21–0
Address
ADDR31–22 PRID
!
The TigerSHARC processor's own internal space (including
UREGs) can be accessed via the multiprocessing space (including
broadcast space) for write transactions only.There are no inter-
locks. Because this is performed through the external bus it should
only be used in special cases where data must pass through the Tig-
erSHARC processor bus interface.
Internal Address Space
The internal address space corresponds to that processor's own internal
address space,
of multiprocessing or internal space. The internal address is
ADDR21–0
divided into three fields, as illustrated in Table 2-4 on page 2-7.
Internal space is the space for transactions within the TigerSHARC pro-
cessor and access to this memory space is not reflected on the cluster bus.
Internal address space is used to access the internal memory blocks, or any
of the Universal registers (Uregs). Universal registers are internal registers
that are mapped to the TigerSHARC processor memory map. Most soft-
ware accessible registers are Uregs.
2-6
Internal address space, as described in "Internal Address Space"
on page 2-6
Processor ID—determine the target processor.
1NNN defines one of eight possible processors, where NNN is
the target TigerSHARC processor ID.
0111 – Broadcast—access (which can be only write) is to all
TigerSHARC processors in the cluster.
0000 – Defines the memory bank as internal
. The internal address space is described by bits
UREGS
ADSP-TS101 TigerSHARC Processor
Hardware Reference
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