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N
Nested Call and Interrupt 1-15
nested calls 1-15
No Boot Mode 10-20
Notation Conventions -xxvii
O
OFIFO 3-6, 5-7, 5-9, 7-13, 7-57,
7-63, 7-67, 10-34
Operating Modes 9-2
operation mode 3-1, 3-2–3-5, 9-2
emulation mode 3-1, 3-2, 3-3–
3-4, 4-10, 4-16, 9-2
supervisor mode 3-1, 3-2, 3-4,
9-2
user mode 3-1, 3-2, 3-5, 9-2
Operation Modes 3-2
Other Interrupt Registers 4-11
Overview 10-1
P
performance monitor 2-23, 3-4,
9-10–9-12
Performance
Monitor
9-12
Performance Monitor Counter –
PRFCNT 2-23
Performance Monitor Mask –
PRFM 2-23, 9-11
Performance Monitors 9-10
Pin Definitions 10-4
Pin State During ACT Command
6-33
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Pin State During MRS Command
6-31
Pin State During PRE Command
6-33
Pin State During Read Command
6-35
Pin State During REF Command
6-42, 6-43
Pin State During Write Command
6-39
Pin States At Reset 10-10
pin states at reset 10-10
Pin Usage 10-8
Pins 9-12
pipe depth 5-49
pipeline 1-7, 1-13, 1-14
Pipelined Protocol 5-15
pipelined protocol 5-1, 5-15, 5-15–
5-26
Counter
Pipelining Transactions 5-18
PMASK Register 2-19, 4-13
PMASK see register
post-modify addressing 1-12
post-modify operator 1-12
Power Supply Sequencing 10-11
Power, Reset and Clock Input
ALU 1-12
basic transaction 5-16–5-18
control signals 5-16
pipe depth 5-16, 5-19, 5-22,
6-2
pipelined
transactions
5-18–5-23, 5-34
wait cycles 5-23–5-26
INDEX
5-2,
xiii
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