Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 256

DMA Transfer Control Block Registers
Table 7-1. DPx Register Bit Descriptions (Cont'd)
Bit Description
Two-Dimensional DMA
2DDMA
Bit27 0 – One-dimensional DMA:
1 – Two-dimensional DMA:
count. The
In this mode of operation, the
ment and count. The
count. When disabled (cleared = 0), the contents of the
ignored, and a normal one-dimensional DMA is performed.
Determines Priority
PR
Bit28 0 – DMA request priority is normal
1 – DMA request priority is high
This bit determines the priority of the DMA. When set (PR = 1), the DMA request
is given a high priority. If the
Access (
pin. If the
nal bus request. When the priority bit is cleared (PR=0), the DMA request priority
is normal. This bit also indicates the priority in the DMA channel arbitration.
Specify the Device Type
TY
Bits31–29 000 – DMA disabled
001 – I/O link port DMA
This type is set when performing link port to link port transfers.
010 – Internal memory
This type must be set in the source
destination of the transfer is internal memory.
011 – Reserved
100 – External memory
The transmitter and receiver
source or destination is in external memory space.
101 – External I/O device (Flyby)
110 – Boot EPROM This type allows for DMA accesses to the boot EPROM mem-
ory. The
111 – Reserved
1 Link channel
TCB
should not be cross chained with any other DMA channels.
7-22
DY
DX
register controls Y dimension addresses, increment, and count.
DY
register controls the Y dimension addresses, increment, and
DY
TCB
) pin is set. See cluster bus definition for more information on the
DPA
refers to an internal address, the DMA asserts its high priority inter-
TCB
TCB
pin is used to select the device when this type is set.
BMS
s field may be programmed with any other link channel. However,
CHTG
register is meaningless
controls X dimension addresses, increment, and
register contains the X dimension addresses, incre-
DX
refers to an external address, then the Priority
if the source is internal memory or if the
TCB
registers should be programmed to this type if the
ADSP-TS101 TigerSHARC Processor
register are simply
DY
DPA
CHTG
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