The host can be a bus master on the TigerSHARC processor's external
bus—it uses
HBR
host to become bus master, the host must assert
asserted by the current TigerSHARC processor master. The TigerSHARC
processor relinquishes the external bus and indicates this by asserting
After completing all outstanding transactions (unless the backoff mecha-
nism is asserted—see "Backoff" on page 5-50), the host keeps
for as long as it needs the bus. The master that last relinquished the bus
keeps its
line asserted, so that when the host deasserts
BR
the master again.
The bus arbitration allows any TigerSHARC processor to gain temporary
priority over the current master. This is achieved by two wired OR pins—
and
.
CPA
DPA
Core Priority Access (CPA)
The Core Priority Access pin,
cessor core accesses external memory. This allows a slave TigerSHARC
processor to interrupt background transfers of a DMA channel belonging
to a master TigerSHARC processor and gain control of the external bus.
The current master in this case terminates its transaction and passes the
bus mastership to the requesting TigerSHARC processor by deasserting its
. When
BR
CPA
tions can request the bus. The other requesting TigerSHARC processors
deassert their
BR
one TigerSHARC processor requests the bus by asserting their
with
, the TigerSHARC processor with the highest priority gains bus
CPA
mastership.
DMA Priority Access (DPA)
The DMA Priority Access,
high priority DMA channel accesses external memory—only if
asserted. This allows a high priority DMA channel belonging to a slave
ADSP-TS101 TigerSHARC Processor
Hardware Reference
and
for gaining control of the bus. In order for the
HBG
CPA
is asserted, only TigerSHARC processors with core transac-
s when they sense that
, is asserted when a TigerSHARC processor
DPA
HBR
, is asserted when the TigerSHARC pro-
is asserted. When more than
CPA
Cluster Bus
and wait until
HBG
HBG
asserted
HBR
, it becomes
HBR
s along
BR
is not
CPA
5-43
is
.
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