Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 237

In order for a DMA channel to be initialized, the program must write to
the DMA channel's Transfer Control Block (
block diagram of the DMA controller.
DMA
REQUESTS
Figure 7-1. DMA Block Diagram
The Transfer Control Block is a quad-word (128-bit) register that con-
tains the vital information required to perform a DMA. The form of the
register is shown in Figure 7-2 on page 7-4.
TCB
In the case of a transmitter
source data, the number of words to be transferred, the address increment
and the control bits.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
TRANSMITTER
TCB
REGISTERS
DMA CONTROLLER
the four words contain the address of the
TCB
Direct Memory Access
). Figure 7-1 shows a
TCB
RECEIVER
TCB
REGISTERS
INTERNAL
BUS
INTERFACE
7-3