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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 to 31 continued on
Figure 2-12
Figure 2-15. BUSLK (Lower) Register Bit Descriptions
BMAX Current Value
This address is read-only and returns the
BMAX Register
The
register is set with the maximum number of internal clock cycles
BMAX
(
) for which the TigerSHARC processor is allowed to retain mastership
CLK
on the external bus. When reading this address, the returned value is the
value written to the
the
register value is 0xFFFF.
BMAX
The BMAX register is automatically loaded after reset and begins to decre-
ment when the TigerSHARC processor attains bus mastership. THe
countdown cannot be disabled. See "Bus Fairness — BMAX" on
page 5-47 for more information. The bit descriptions for this register are
shown in Figure 2-16 on page 2-40 and Figure 2-17 on page 2-41.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
register, not the current cycle count. After reset,
BMAX
Memory and Register Map
BUSLK When this bit is set, the processor
requests the bus and holds it for as long
as the bit remains set.
Reserved
counter value when read.
BMAX
2-39
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