It is important to set the Address Pointer registers first (before the
register) which define the actual watchpoint operation. The address regis-
ters of a watchpoint cannot be changed when the watchpoint is active.
A watchpoint operation is defined by its Control register—
i is 0, 1, or 2 for different watchpoints).
follows.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-2. WPxCTL (Lower) Register Bit Descriptions
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Debug Functionality
registers are configured as
WPiCTL
OPMODE Type of watchpoint operation
BM Bus Master Selections
R If set, read to memory transactions are
monitored.
W If set, write to memory transactions are
monitored.
EXTYPE Write
SSTP/WPOR/WPAND Watchpoint register OR
and AND bits
Reserved
WPiCTL
(where
WPiCTL
9-5
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